• Select at least six distinct, non-overlapping classes of semiconductor manufacturing defects (for example: shorts, opens, bridges, malformed vias, CMP scratches, cracks, LER, etc.; refer to the reference section for sample images). In addition to these defect classes, include the categories “Clean” and “Other”, resulting in a minimum of eight total classes.
• Gather images representing both clean and defective samples from any available source to build your own dataset. No dataset will be provided during the Hackathon, except in Phase 2, where a test dataset will be supplied exclusively for prediction.
• Ensure the dataset includes a minimum of 500 images covering clean, defective, and “Other” categories, with a well-balanced distribution across all classes. For improved model performance, a dataset of more than 1,000 images is recommended.
• Prefer using black-and-white (single-channel) images; color images are not recommended.

• Use Python for development.
• Framework: TensorFlow, PyTorch, or any other AI framework (allowed).
• Training approach: from scratch or transfer learning (allowed).
• Target: achieve good accuracy with low model size and high portability for edge deployment.

• Port the trained model using the NXP eIQ platform targeting NXP i.MX RT series devices.
• No hardware or board demo is in scope; the process ends at generation of deployment artifacts or bit-file outputs as per the defined flow.
• Technical support from Hackathon organizers for this step is limited to online documentation.

• Document the end-to-end approach, including innovation highlights, challenges faced, and future scope.
• Present the solution in a clear and structured manner covering dataset, model, evaluation, edge porting, and impact.

Teams must submit the following (as applicable by phase):

1. Document describing problem understanding, approach, dataset plan, model plan, etc., as provided in the template. Submit a filled PDF document.
2. Dataset: a single .zip file of images with class categories. Follow the folder structure to group images into Train, Validation, and Test folders, each containing sub-folders for “clean”, “other”, “defect class Name_1”, “defect class Name_2” … “defect class Name_N”.
3. Trained ML model in ONNX format.
4. Model results on your test set, including Accuracy, Precision, Recall, Confusion Matrix, Model size, Algorithm used, and platform used for training and inference.
   
   • Note: If GPUs or cloud infrastructure were used, please specify.
   • Note: The model may be built from scratch or using pre-trained models with transfer learning.
5. GitHub repository link (mandatory) with a README and complete development code.
6. Model results on the hackathon test set, including Accuracy, Precision, Recall, and Confusion Matrix.
7. NXP eIQ ported model results provided as a text file of the instruction stack (as per eIQ documentation).
8. Complete code covering preprocessing, training, and inference.
9. Final documentation addressing the end-to-end solution, covering development and learnings from all stages.

Evaluation Data Rule: After the phase-1 submission deadline, the submitted model becomes the
reference model, and no re-submission is allowed. Teams then proceed to next steps and edge-
porting.

• The hackathon is aimed at an intermediate development level, positioned between a prototype and a fully functional solution. Participants are encouraged to explore diverse ideas and demonstrate creativity in their approach to the challenge.
• During Phase 1, participants are encouraged to prepare for Phase 3 by pre-reviewing requirements related to compatibility, portability, and model conversion formats.
• For Phase 3, no hardware boards will be provided as part of the hackathon. The phase concludes with the generation of a bit-file. Support for Phase 3 is limited to existing online documentation, and no additional support will be provided.

• 
  NXP eIQ Toolkit – AI development environment for end-to-end model development and deployment
  
• 
  Sample images and documentation – Defect Classification System for Semiconductor Sample Images